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| Features * 3.0V to 3.6V Operating Range * Advanced, High-speed, Electrically-erasable Programmable Logic Device - Superset of 22V10 - Enhanced Logic Flexibility - Architecturally Compatible with ATV750B and ATV750 Software and Hardware D- or T-type Flip-flop Product Term or Direct Input Pin Clocking 15 ns Maximum Pin-to-pin Delay with 3V Operation Highest Density Programmable Logic Available in 24-pin Package - Advanced Electrically-erasable Technology - Reprogrammable - 100% Tested Increased Logic Flexibility - 42 Array Inputs, 20 Sum Terms and 20 Flip-flops Enhanced Output Logic Flexibility - All 20 Flip-flops Feed Back Internally - 10 Flip-flops are also Available as Outputs Programmable Pin-keeper Circuits Dual-in-line and Surface Mount Package in Standard Pinouts Commercial and Industrial Temperature Ranges 20-year Data Retention 2000V ESD Protection 1000 Erase/Write Cycles * * * * * * * * * * * * High-speed Complex Programmable Logic Device ATF750LVC Block Diagram (OE PRODUCT TERMS) 12 INPUT PINS PROGRAMMABLE INTERCONNECT AND COMBINATORIAL LOGIC ARRAY 4 TO 8 PRODUCT TERMS LOGIC OPTION (UP T0 20 FLIP-FLOPS) OUTPUT OPTION 10 I/O PINS (CLOCK PIN) Description The Atmel "750" architecture is twice as powerful as most other 24-pin programmable logic devices. Increased product terms, sum terms, flip-flops and output logic configurations translate into more usable gates. High-speed logic and uniform, predictable delays guarantee fast in-system performance. The ATF750LVC is a high-performance Pin Configurations Pin Name CLK IN I/O GND VCC Note: Function Clock Logic Inputs Bi-directional Buffers Ground 3V Supply For PLCC, pins 1, 8, 15, and 22 can be left unconnected. For superior performance, connect VCC to pin 1 and GND to pins 8, 15, and 22. (continued) DIP/SOIC/TSSOP CLK/IN IN IN IN IN IN IN IN IN IN IN GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O IN PLCC IN IN CLK/IN VCC * VCC I/O I/O 4 3 2 1 28 27 26 IN IN GND GND * IN I/O I/O 12 13 14 15 16 17 18 IN IN IN GND * IN IN IN 5 6 7 8 9 10 11 25 24 23 22 21 20 19 I/O I/O I/O GND * I/O I/O I/O Rev. 1447D-03/01 1 CMOS (electrically-erasable) complex programmable logic device (CPLD) that utilizes Atmel's proven electrically-erasable technology. Each of the ATF750LVC's 22 logic pins can be used as an input. Ten of these can be used as inputs, outputs or bidirectional I/O pins. Each flip-flop is individually configurable as either D- or T-type. Each flip-flop output is fed back into the array independently. This allows burying of all the sum terms and flip-flops. There are 171 total product terms available. There are two sum terms per output, providing added flexibility. A variable format is used to assign between four to eight product terms per sum term. Much more logic can be replaced by this device than by any other 24-pin PLD. With 20 sum terms and flip-flops, complex state machines are easily implemented with logic to spare. Product terms provide individual clocks and asynchronous resets for each flip-flop. Each flip-flop may also be individually configured to have direct input pin controlled clocking. Each output has its own enable product term. One product term provides a common synchronous preset for all flipflops. Register preload functions are provided to simplify testing. All registers automatically reset upon power-up. Absolute Maximum Ratings* Temperature Under Bias.................................. -40C to +85C Storage Temperature ..................................... -65C to +150C Voltage on Any Pin with Respect to Ground .........................................-2.0V to +4.6V(1) Voltage on Input Pins with Respect to Ground During Programming.....................................-2.0V to +14.0V(1) Note: Programming Voltage with Respect to Ground .......................................-2.0V to +14.0V(1) 1. *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Minimum voltage is -0.6V DC, which may undershoot to -2.0V for pulses of less than 20 ns. Maximum output pin voltage is VCC + 0.75V DC, which may overshoot to 4.6V for pulses of less than 20 ns. DC and AC Operating Conditions 3.3V Operation Operating Temperature (Ambient) VCC Power Supply Commercial 0C - 70C 3.0 - 3.6V Industrial -40C - +85C 3.0 -=3.6V 2 ATF750LVC ATF750LVC Clock Mux CKMUX CKi CLOCK PRODUCT TERM CLK PIN TO LOGIC CELL SELECT Output Options Bus-friendly Pin-keeper Input and I/Os All input and I/O pins on the ATF750LVC(L) have programmable "pin-keeper" circuits. If activated, when any pin is driven high or low and then subsequently left floating, it will stay at that previous high or low level. This circuitry prevents unused input and I/O lines from floating to intermediate voltage levels, which cause unnecessary power consumption and system noise. The keeper circuits eliminate the need for external pull-up resistors and eliminate their DC power consumption. Enabling or disabling of the pin-keeper circuits is controlled by the device type chosen in the logic compiler device selection menu. Please refer to the software compiler table for more details. Once the pin-keeper circuits are disabled, normal termination procedures are required for unused inputs and I/Os. Table 1. Software Compiler Mode Selection Synario ATF750LVC ATF750LVC (PPK) Wincupl V750C V750CPPK Pin-keeper Circuit Disabled Enabled Input Diagram VCC INPUT 100K ESD PROTECTION CIRCUIT PROGRAMMABLE OPTION I/O Diagram VCC OE DATA I/O VCC 100K PROGRAMMABLE OPTION 3 DC Characteristics Symbol ILI ILO Parameter Input Load Current Output Leakage Current Power Supply Current, Standby Output Short Circuit Current Input Low Voltage Input High Voltage IOL = 16 mA VOL Output Low Voltage Output High Voltage VIN = VIH or VIL, VCC = Min VIN = VIH or VIL, VCC = Min IOL = 12 mA IOL = 24 mA VOH Notes: IOH = -2.0 mA Com., Ind. Mil. Com. 2.4 Condition VIN = -0.1V to VCC + 1V VOUT = -0.1V to VCC + 0.1V VCC = Max, VIN = Max, Outputs Open Com. C-15 Ind. 70 100 mA 65 Min Typ Max 10 10 90 Units A A mA ICC IOS(1)(2) VIL VIH VOUT = 0.5V 3.0 VCC 3.6V -0.6 2.0 -120 0.8 VCC + 0.75 0.5 0.5 0.8 mA V V V V V V 1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec. 2. This test is performed at initial characterisation only. Input Test Waveforms and Measurement Levels Output Test Load VCC 316 348 tR, tF < 3 ns (10% to 90%) 4 ATF750LVC ATF750LVC AC Waveforms, Product Term Clock(1) Note: 1. Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise specified. AC Characteristics, Product Term Clock(1) -15 Symbol tPD tEA tER tCO tCF tS tSF tH tP tW Parameter Input or Feedback to Non-registered Output Input to Output Enable Input to Output Disable Clock to Output Clock to Feedback Input Setup Time Feedback Setup Time Hold Time Clock Period Clock Width External Feedback 1/(tS + tCO) fMAX Internal Feedback 1/(tSF + tCF) No Feedback 1/(tP) tAW tAR tAP tSP Note: Asynchronous Reset Width Asynchronous Reset Recovery Time Asynchronous Reset to Registered Output Reset Setup Time, Synchronous Preset 1. See ordering information for valid part numbers. 8 15 15 15 5 5 8 7 5 14 7 50 62 71 Min Max 15 15 15 12 9 Units ns ns ns ns ns ns ns ns ns ns MHz MHz MHz ns ns ns ns 5 AC Waveforms, Input Pin Clock(1) Notes: 1. Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise specified. AC Characteristics, Input Pin Clock -15 Symbol tPD tEA tER tCOS tCFS tSS tSFS tHS tPS tWS Parameter Input or Feedback to Non-registered Output Input to Output Enable Input to Output Disable Clock to Output Clock to Feedback Input Setup Time Feedback Setup Time Hold Time Clock Period Clock Width External Feedback 1/(tSS + tCOS) fMAXS Internal Feedback 1/(tSFS + tCFS) No Feedback 1/(tPS) tAW tARS tAP tSPS Asynchronous Reset Width Asynchronous Reset Recovery Time Asynchronous Reset to Registered Output Reset Setup Time, Synchronous Preset 11 15 15 15 0 0 8 7 0 12 6 55 80 83 Min Max 15 15 15 10 5.5 Units ns ns ns ns ns ns ns ns ns ns MHz MHz MHz ns ns ns ns 6 ATF750LVC ATF750LVC Functional Logic Diagram ATF750LVC, Upper Half 7 Functional Logic Diagram ATF750LVC, Lower Half 8 ATF750LVC ATF750LVC Using the ATF750LVC's Many Advanced Features The ATF750LVC's advanced flexibility packs more usable gates into 24-pins than any other logic device. The ATF750LVCs start with the popular 22V10 architecture, and add several enhanced features: * Selectable D- and T-type Registers Each ATF750LVC flip-flop can be individually configured as either D- or T-type. Using the T-type configuration, JK and SR flip-flops are also easily created. These options allow more efficient product term usage. * Selectable Asynchronous Clocks Each of the ATF750LVC's flip-flops may be clocked by its own clock product term or directly from Pin 1 (SMD Lead 2). This removes the constraint that all registers must use the same clock. Buried state machines, counters and registers can all coexist in one device while running on separate clocks. Individual flip-flop clock source selection further allows mixing higher performance pin clocking and flexible product term clocking within one design. * A Full Bank of Ten More Registers The ATF750LVC provides two flip-flops per output logic cell for a total of 20. Each register has its own sum term, its own reset term and its own clock term. * Independent I/O Pin and Feedback Paths Each I/O pin on the ATF750LVC has a dedicated input path. Each of the 20 registers has its own feedback terms into the array as well. This feature, combined with individual product terms for each I/O's output enable, facilitates true bi-directional I/O design. Synchronous Preset and Asynchronous Reset One synchronous preset line is provided for all 20 registers in the ATF750LVC. The appropriate input signals to cause the internal clocks to go to a high state must be received during a synchronous preset. Appropriate setup and hold times must be met, as shown in the switching waveform diagram. An individual asynchronous reset line is provided for each of the 20 flip-flops. Both master and slave halves of the flipflops are reset when the input signals received force the internal resets high. Security Fuse Usage A single fuse is provided to prevent unauthorized copying of the ATF750LVC fuse patterns. Once the security fuse is programmed, all fuses will appear programmed during verify. The security fuse should be programmed last, as its effect is immediate. 9 OUTPUT SOURCE CURRENT VS SUPPLY VOLTAGE (VOH = 2.4V, TA = 25C) 0.0 -1.0 -2.0 IOH (mA) -3.0 -4.0 -5.0 -6.0 -7.0 -8.0 3.00 3.25 3.30 SUPPLY VOLTAGE (V) 3.50 3.60 OUTPUT SINK CURRENT VS SUPPLY VOLTAGE (VOL = 0.5V, TA = 25C) 24.0 23.0 22.0 IOL (mA) 21.0 20.0 19.0 18.0 17.0 16.0 3.00 3.25 3.30 SUPPLY VOLTAGE (V) 3.50 3.60 INPUT CURRENT VS INPUT VOLTAGE (VCC = 3.3V, TA = 25C) 15.0 10.0 5.0 0.0 -5.0 -10.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 INPUT VOLTAGE (V) INPUT CURRENT (mA) 0.0 -10.0 INPUT CLAMP CURRENT VS INPUT VOLTAGE (VCC = 3.3V, T A = 25C) INPUT CURRENT (A) -20.0 -30.0 -40.0 -50.0 -60.0 -70.0 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 INPUT VOLTAGE (V) SUPPLY CURRENT VS SUPPLY VOLTAGE (T A = 25C) 70.0 60.0 ICC (mA) 50.0 40.0 30.0 3.0 3.3 SUPPLY VOLTAGE (V) 3.6 10 ATF750LVC ATF750LVC OUTPUT SOURCE CURRENT VS OUTPUT VOLTAGE (VCC = 3.3V, TA = 25C) 0.0 -10.0 -20.0 IOH (mA) -30.0 -40.0 -50.0 -60.0 -70.0 0.0 0.5 1.0 1.5 VOH (V) 2.0 2.5 3.0 3.3 IOL (mA) 50.0 40.0 30.0 20.0 10.0 0.0 0.0 80.0 70.0 60.0 OUTPUT SOURCE SINK CURRENT VS OUTPUT VOLTAGE (VCC = 3.3V, TA = 25C) 0.5 1.0 1.5 VOL (V) 2.0 2.5 3.0 3.3 SUPPLY CURRENT VS INPUT FREQUENCY (VCC = 5.00V, TA = 25C) 80 ICC (mA) 40 0 0 5 10 15 20 50 75 100 FREQUENCY (MHz) 11 ATF750LVC Ordering Information tPD (ns) 15 tCOS (ns) 10 Ext. fMAXS (MHz) 55 Ordering Code ATF750LVC-15JC ATF750LVC-15PC ATF750LVC-15SC ATF750LVC-15XC(1) ATF750LVC-15JI ATF750LVC-15PI ATF750LVC-15SI ATF750LVC-15X(1)I Package 28J 24P3 24S 24X(1) 28J 24P3 24S 24X(1) Operation Range Commercial (0C to 70C) Industrial (-40C to 85C) Note: 1. Special order only; TSSOP package requires special thermal management. Using "C" Product for Industrial Because the VCC conditions are the same for commercial and industrial for 3.3V products, and there is only 15C difference at the high end of the temperature range, there is very little risk in using "C" devices for industrial applications. Just de-rate ICC by 15%. Package Type 28J 24P3 24S 24X* 28-Lead, Plastic J-leaded Chip Carrier (PLCC) 24-lead, 0.300' Wide, Plastic Dual Inline Package (PDIP) 24-lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC) 24-lead, 0.173" Wide, Thin Shrink Small Outline (TSSOP) 12 ATF750LVC ATF750LVC Packaging Information 28J, 28-lead, Plastic J-leaded Chip Carrier (PLCC) Dimensions in Inches and (Millimeters) JEDEC STANDARD MS-018 AB 24P3, 24-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) Dimensions in Inches and (Millimeters) JEDEC STANDARD MS-001 AF 1.27(32.3) 1.25(31.7) .045(1.14) X 45 PIN NO. 1 IDENTIFY .045(1.14) X 30 - 45 .012(.305) .008(.203) PIN 1 .266(6.76) .250(6.35) .090(2.29) MAX .005(.127) MIN .032(.813) .026(.660) .456(11.6) SQ .450(11.4) .495(12.6) SQ .485(12.3) .300(7.62) REF SQ .430(10.9) SQ .390(9.91) .021(.533) .013(.330) .200(5.06) MAX SEATING PLANE .151(3.84) .125(3.18) .110(2.79) .090(2.29) 1.100(27.94) REF .050(1.27) TYP .043(1.09) .020(.508) .120(3.05) .090(2.29) .180(4.57) .165(4.19) .070(1.78) .020(.508) .023(.584) .014(.356) .065(1.65) .040(1.02) .325(8.26) .300(7.62) .022(.559) X 45 MAX (3X) .012(.305) .008(.203) 0 REF 15 .400(10.2) MAX 24S, 24-lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC) Dimensions in Inches and (Millimeters) 24X, 24-lead, 0.173" Wide, Thin Shrink Small Outline (TSSOP) Dimensions in Millimeters and (Inches)* .020(.508) .013(.330) .299(7.60) .420(10.7) .291(7.39) .393(9.98) PIN 1 ID .050(1.27) BSC .616(15.6) .598(15.2) .105(2.67) .092(2.34) .012(.305) .003(.076) .013(.330) .009(.229) 0 REF 8 .050(1.27) .015(.381) *Controlling dimension: millimeters 13 Atmel Headquarters Corporate Headquarters 2325 Orchard Parkway San Jose, CA 95131 TEL (408) 441-0311 FAX (408) 487-2600 Atmel Operations Atmel Colorado Springs 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TEL (719) 576-3300 FAX (719) 540-1759 Europe Atmel U.K., Ltd. Coliseum Business Centre Riverside Way Camberley, Surrey GU15 3YL England TEL (44) 1276-686-677 FAX (44) 1276-686-697 Atmel Rousset Zone Industrielle 13106 Rousset Cedex France TEL (33) 4-4253-6000 FAX (33) 4-4253-6001 Atmel Smart Card ICs Scottish Enterprise Technology Park East Kilbride, Scotland G75 0QR TEL (44) 1355-803-000 FAX (44) 1355-242-743 Asia Atmel Asia, Ltd. Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimhatsui East Kowloon Hong Kong TEL (852) 2721-9778 FAX (852) 2722-1369 Atmel Grenoble Avenue de Rochepleine BP 123 38521 Saint-Egreve Cedex France TEL (33) 4-7658-3000 FAX (33) 4-7658-3480 Japan Atmel Japan K.K. 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan TEL (81) 3-3523-3551 FAX (81) 3-3523-7581 Fax-on-Demand North America: 1-(800) 292-8635 International: 1-(408) 441-0732 literature@atmel.com Web Site http://www.atmel.com BBS 1-(408) 436-4309 (c) Atmel Corporation 2001. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life suppor t devices or systems. Marks bearing (R) and/or TM are registered trademarks and trademarks of Atmel Corporation. Printed on recycled paper. 1447D-03/01/xM Terms and product names in this document may be trademarks of others. |
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